View FAN4800AUN_7199431.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 2011 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 fan4800au/cu ? pfc/ pwm controller combination fan4800au/cu pfc/ pwm controller combination features ? pin-to-pin compatible with ml4800, fan4800, cm6800, and cm6800a ? pwm configurable for current-mode or feed-forward voltage-mode operation ? internally synchronized leading-edge pfc and trailing-edge pwm in one ic ? low operating current ? innovative switching-char ge multiplier divider ? average-current-mode for input-current shaping ? pfc over-voltage and under-voltage protections ? pfc feedback open-loop protection ? cycle-by-cycle current limiting for pfc/pwm ? power-on sequence control and soft-start ? line sagging protection ? f rtct =4?f pfc =4?f pwm for fan4800au ? f rtct =4?f pfc =2?f pwm for fan4800cu applications ? desktop pc power supply ? internet server power supply ? lcd tv/ monitor power supply ? ups ? battery charger ? dc motor power supply ? monitor power supply ? telecom system power supply ? distributed power related resources ? an-8027 ? fan480x pfc+pwm combination controller application description the highly integrated fan4800au/cu parts are specially designed for power supplies that consist of boost pfc and pwm. they require very few external components to achieve versatile protections and compensation. they are available in 16-pin dip and sop packages. the pwm can be used in curr ent or voltage mode. in voltage mode, feed-forward from the pfc output bus can reduce secondary output ripple. to evaluate fan4800au/cu for replacing existing fan4800a/c, fan4800as/cs, old version fan4800 and ml4800 boards, six things must be completed before the fine-tuning procedure: 1. change r ac resistor from the old value to a higher resistor value: 6m ? to 8m ? . 2. change rt/ct pin from the existing values to r t =6.8k ? and c t =1000pf to have f pfc =64khz and f pwm =64khz. 3. the vrms pin needs to be 1.224v at v in =85v ac for universal input application with line input from 85v ac to 270 v ac . 4. change isense pin filter from the exiting values to r filter =51 ? and c filter =0.01f for higher bandwidth. 5. at full load, the average v vea must be ~4.5v and ripple on v vea needs to be less than 400mv. 6. for the ss pin, the so ft-start current has been reduced to half the fan4800 capacitor. there are two differences from fan4800as/cs to fan4800au/cu: ? add line sagging protection ? fix inductance current instability during ac cycle drop test
fan4800au/cu ? pfc/ pwm controller combination ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 ordering information part number operating temperature range pfc:pwm frequency ratio package packing method FAN4800AUN -40c to +105c 1:1 16-pin dual inline package (dip) tube fan4800cun 1:2 fan4800aum 1:1 16-pin small outline package (sop) tape & reel fan4800cum 1:2 block diagram figure 1. function block diagram
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 3 fan4800au/cu ? pfc/ pwm controller combination application diagrams ac iea ilimit fbpwm ss isense iac gnd opfc vdd fbpfc vea v dd opwm l boost c bulk d boost r sense r filter 12v 5v fbpwm r fb1 r d c fb 1nf fbpwm c filter c vin 10 ? 10k ? q1 r fbpfc1 r fbpfc2 r fbpfc3 c fbpfc 10 ? 10k ? 10k ? q2 q3 d f1 d f2 r iea c iea1 c iea2 r vea c vea1 c vea2 c ss r ilimit r filter c filter c vdd l m r fb2 r fb3 10 ? vref 47nf vrms rt/ct ramp r fb4 3m ? 3m ? 1m ? 1m ? 200k ? 36k ? 220nf r fbpwm r ramp c ramp r t c t 12v 5v figure 2. current mode ac iea ilimit fbpwm ss isense iac gnd opfc vdd fbpfc vea v dd opwm l boost c bulk d boost r sense r filter 12v 5v fbpwm r fb1 r d c fb 1nf fbpwm c filter c vin 10 ? 10k ? q1 r fbpfc1 r fbpfc2 r fbpfc3 c fbpfc 10 ? 10k ? 10k ? q2 q3 d f1 d f2 r iea c iea1 c iea2 r vea c vea1 c vea2 c ss r ilimit r filter c filter c vdd l m r fb2 r fb3 10 ? vref 47nf vrms rt/ct ramp r fb4 3m ? 3m ? 1m ? 1m ? 200k ? 36k ? 220nf r fbpwm r ramp c ramp r t c t 12v 5v figure 3. voltage mode
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 4 fan4800au/cu ? pfc/ pwm controller combination marking information figure 4. dip top mark figure 5. sop top mark f ? fairchild logo z ? plant code x ? 1-digit year code yy ? 2-digit week code tt ? 2-digit die-run code t ? package type (n:dip) m ? manufacture flow code f ? fairchild logo z ? plant code x ? 1-digit year code y ? 1-digit week code tt ? 2-digit die-run code t ? package type (m:sop) m ? manufacture flow code
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 5 fan4800au/cu ? pfc/ pwm controller combination pin configuration figure 6. pin configuration (top view ) pin definitions pin # name description 1 iea output of pfc current amplifier . the signal from this pin is compared with an internal sawtooth to determine the pulse width for the pfc gate drive. 2 iac input ac current . for normal operation, this input prov ides a current reference for the multiplier. the suggested maximum i ac is 65a. 3 isense pfc current sense . the inverting input of the pfc cu rrent amplifier and the output of multiplier and pfc i limit comparator. 4 vrms line-voltage detection . the pin is used for the pfc multiplier. 5 ss pwm soft-start . during startup, the ss pin charges an ex ternal capacitor with a 10a constant current source. the voltage on fbpwm is cl amped by ss during startup. if a protection condition occurs and/or pwm is disabled, the ss pin is quickly discharged. 6 fbpwm pwm feedback input . the control input for voltage-loop feedback of pwm stage. 7 rt/ct oscillator rc timing connection . oscillator timing node; timing set by r t and c t . 8 ramp pwm ramp input . in current mode, this pin functions as the current-sense input. in voltage mode, it is the feed-forward sense input from pfc output 380v (feed-forward ramp). 9 ilimit peak current limit setting for pwm . the peak current limit setting for pwm. 10 gnd ground 11 opwm pwm gate drive . the totem-pole output drive for the pwm mosfet. this pin is internally clamped under 19v to protect the mosfet. 12 opfc pfc gate drive . the totem-pole output drive for pfc mosfet. this pin is internally clamped under 15v to protect the mosfet. 13 vdd supply . the power supply pin. the threshold volt ages for startup and turn-off are 11v and 9.3v, respectively. the operating current is lower than 10ma. 14 vref reference voltage . buffered output for the internal 7.5v reference. 15 fbpfc voltage feedback input for pfc . the feedback input for pfc volt age loop. the inverting input of pfc error amplifier. this pin is connect ed to the pfc output through a divider network. 16 vea output of pfc voltage amplifier . the error amplifier output for pfc voltage feedback loop. a compensation network is connected between this pin and ground.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 6 fan4800au/cu ? pfc/ pwm controller combination absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage 30 v v h voltage on ss, fbpwm, ramp, vref pins -0.3 30.0 v v pfc-out voltage on opfc pin v dd +0.3v v v pwm-out voltage on opwm pin v dd +0.3v v v l voltage on iac, vrms, rt/ct, ilimit, fbpfc, vea pins -0.3 7.0 v v iea voltage on iea pin 0 v vref +0.3 v v n voltage on isense pin -5.0 0.7 v i ac input ac current 1 ma i ref vref output current 5 ma i pfc-out peak pfc out current, source or sink 0.5 a i pwm-out peak pwm out current, source or sink 0.5 a p d power dissipation t a < 50c 800 mw ja thermal resistance (junction to air) dip 80.80 c/w sop 104.10 jc thermal resistance (junction to case) dip 35.38 c/w sop 40.41 t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature(soldering) +260 c esd electrostatic discharge capability human body model, jesd22-a114 6.0 kv charged device model, jesd22-c101 2.0 notes: 1. all voltage values, except differential vo ltage, are given with respect to gnd pin. 2. stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating ambient tem perature -40 +105 c
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 7 fan4800au/cu ? pfc/ pwm controller combination electrical characteristics unless otherwise noted, v dd =15v, t a = 25c, t a =t j , r t =6.8k ? , and c t =1000pf . symbol parameter condition min. typ. max. unit v dd section i dd-st startup current v dd =v th-on -0.1v, opfc opwm open 30 80 a i dd-op operating current v dd =13v, opfc opwm open 2.0 2.6 5.0 ma v th-on turn-on threshold voltage 10 11 12 v v th hysteresis 1.3 1.9 v v dd-ovp v dd ovp 27 28 29 v v dd-ovp v dd ovp hysteresis 1 v oscillator f osc-rt/ct rt/ct frequency r t =6.8k ? , c t =1000pf 240 256 268 khz f osc pfc & pwm frequency 60 64 67 khz fan4800cu pwm frequency 120 128 134 f dv voltage stability (3) 11v Q v dd Q 22v 2 % f dt temperature stability (3) -40c ~ +105c 2 % f tv total variation (pfc & pwm) (3) line, temperature 58 70 khz f rv ramp voltage valley to peak 2.8 v i osc-dis discharge current v ramp =0v, v rt/ct =2.5v 6.5 15.0 ma f range frequency range 50 75 khz t pfc-dead pfc dead time r t =6.8k ? , c t =1000pf 400 600 800 ns v vref v vref reference voltage i vref =0ma, c vref =0.1f 7.4 7.5 7.6 v v vref1 load regulation of reference voltage c vref =0.1f, i vref =0ma to 3.5ma v dd =14v, rise/fall time > 20s 30 50 mv v vref2 line regulation of reference voltage c vref =0.1f, v dd =11v to 22v 25 mv v vref-dt temperature stability (3) -40c ~ +105c 0.4 0.5 % v vref-tv total variation (3) line, load, temperature 7.35 7.65 v v vref-ls long-term stability (3) t j =125c, 0 ~ 1000 hours 5 25 mv i vref-max . maximum current v vref > 7.35v 5 ma pfc ovp comparator v pfc-ovp over-voltage protection 2.70 2.75 2.80 v v pfc-ovp pfc ovp hysteresis 200 250 300 mv low-power detect comparator v veaoff vea voltage off opfc 0.2 0.3 0.4 v v in ok comparator v rd-fbpfc voltage level on fbpfc to enable opwm during startup 2.3 2.4 2.5 v v rd-fbpfc hysteresis 1.0 1.1 1.2 v continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 8 fan4800au/cu ? pfc/ pwm controller combination electrical characteristics (continued) unless otherwise noted, v dd =15v, t a = 25c, t a =t j , r t =6.8k ? , and c t =1000pf . symbol parameter condition min. typ. max. unit voltage error amplifier v ref reference voltage 2.45 2.50 2.55 v a v open-loop gain (3) 35 42 db gm v transconductance v noninv =v inv , v vea =3.75v 50 70 90 mho i fbpfc-l maximum source current v fbpfc =2v, v vea =1.5v 40 50 a i fbpfc-h maximum sink current v fbpfc =3v, v vea =6v -50 -40 a i bs input bias current -1 1 a v vea-h output high voltage on v vea 5.8 6.0 v v vea-l output low voltage on v vea 0.1 0.4 v current error amplifier gm i transconductance v noninv =v inv , v iea =3.75v 70 88 105 mho v offset input offset voltage v vea =0v, iac open -10 10 mv v iea-h output high voltage 6.8 7.4 7.8 v v iea-l output low voltage 0.1 0.4 v i l source current v isense = -0.6v, v iea =1.5v 35 50 a i h sink current v isense = +0.6v, v iea =4.0v -50 -35 a a i open-loop gain (3) 40 50 db trifault detect? t fbpfc-open time to fbpfc open v fbpfc =v pfc-uvp to fbpfc open, 470pf from fbpfc to gnd 2 4 ms v pfc-uvp pfc feedback under-voltage protection 0.4 0.5 0.6 v gain modulator i ac input for ac current (3) multiplier linear range 0 65 a gain gain modulator (4) i ac =17.67a, v rms =1.080v v fbpfc =2.25v 7.94 i ac =20a, v rms =1.224v v fbpfc =2.25v 7.02 i ac =25.69a, v rms =1.585v v fbpfc =2.25v 4.18 i ac =51.62a, v rms =3.169v v fbpfc =2.25v 1.05 i ac =62.23a, v rms =3.803v v fbpfc =2.25v 0.73 bw bandwidth (3) i ac =40a 2 khz v o (gm) output voltage=5.7k ? (i sense -i offset ) i ac =50a, v rms =1.224v v fbpfc =2.25v 0.76 0.80 0.84 v pfc i limit comparator v pfc-ilimit peak current limit threshold voltage, cycle-by-cycle limit -1.2 -1.3 -1.4 v v pk pfc i limit -gain modulator output i ac =17.67a, v rms =1.08v v fbpfc =2.25v 400 mv continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 9 fan4800au/cu ? pfc/ pwm controller combination electrical characteristics (continued) unless otherwise noted, v dd =15v, t a = 25c, t a =t j , r t =6.8k ? , and c t =1000pf . symbol parameter condition min. typ. max. unit pfc output driver v gate-clamp gate output clamping voltage v dd =22v 13 15 17 v v gate-l gate low voltage v dd =15v, i o =100ma 1.5 v v gate-h gate high voltage v dd =13v, i o =100ma 8 v t r gate rising time v dd =15v, c l =4.7nf, o/p= 2v to 9v 40 70 120 ns t f gate falling time v dd =15v, c l =4.7nf, o/p=9v to 2v 40 60 110 ns d pfc-max maximum duty cycle v iea <1.2v 94 97 % d pfc-min minimum duty cycle v iea >4.5v 0 % pwm i limit comparator v pwm-ilimit threshold voltage 0.95 1.00 1.05 v t pd propagation delay to output 250 ns t pwm-bnk leading-edge blanking time 170 250 350 ns pwm output driver v gate-clamp gate output clamping voltage v dd =22v 18 19 20 v v gate-l gate low voltage v dd =15v, i o =100ma 1.5 v v gate-h gate high voltage v dd =13v, i o =100ma 8 v t r gate rising time v dd =15v, c l =4.7nf, o/p=2v to 9v 30 60 120 ns t f gate falling time v dd =15v, c l =4.7nf, o/p=9v to 2v 30 50 110 ns d pwm-max maximum duty cycle 49.0 49.5 50.0 % v pwm-ls pwm comparator level shift 1.3 1.5 1.8 v soft-start v ss-max maximum voltage v dd =15v 9.5 10.0 10.5 v i ss soft-start current 10 a brownout v rms-uvl vrms threshold low 1.00 1.05 1.10 v v rms-uvh vrms threshold high 1.85 1.90 1.95 v v rms-uvp hysteresis 750 850 950 mv t uvp under- voltage protection delay 750 1000 1250 ms sagging protection v rms-sag vrms threshold sag low 0.80 0.85 0.90 v t sag sag protection delay 28 33 38 ms notes: 3. this parameter, although guaranteed by design, is not 100% production tested. 4. this gain is the maximum gain of modulation with a given v rms voltage when v vea is saturated to high.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 10 fan4800au/cu ? pfc/ pwm controller combination typical characteristics figure 7. i dd-st vs. temperature figure 8. v dd-ovp vs. temperature figure 9. f osc vs. temperature figure 10. v vref vs. temperature figure 11. v pfc-ovp vs. temperature figure 12. v ref vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 11 fan4800au/cu ? pfc/ pwm controller combination typical characteristics figure 13. gm v vs. temperature figure 14. gm i vs. temperature figure 15. v pfc-ilimit vs. temperature figure 16. v pwm-ilimit vs. temperature figure 17. v rms-uvp vs. temperature figure 18. ?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 12 fan4800au/cu ? pfc/ pwm controller combination typical characteristics figure 19. v gate-clamp-pfc vs. temperature figure 20. v gate-clamp-pwm vs. temperature figure 21. d pfc-max vs. temperature figure 22. d pwm-max vs. temperature figure 23. i ss vs. temperature figure 24. v rms-sag vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 13 fan4800au/cu ? pfc/ pwm controller combination functional description oscillator the internal oscillator frequency is determined by the timing resistor and capacitor on the rt/ct pins as shown in figure 25. the frequency of the internal oscillator is given: t t t osc c c r f 360 56 . 0 1 ? ? ? ? (1) because the pwm stage generally uses a forward converter, it is necessary to limit the maximum duty cycle at 50%. to have a small tolerance of the maximum duty cycle, a frequency divider with toggle flip-flops is used, as il lustrated in figure 25. the operation frequency of pfc and pwm stage is 1/4 of oscillator frequency. (for fan4800cu, the operation frequencies for pfc and pwm stages are 1/4 and 1/2 of oscillator frequency, respectively). the dead time for the pfc gate drive signal is determined by: t dead c t 360 ? (2) the dead time should be smaller than 2% of the switching period to minimize line current distortion around the line zero crossing. figure 25. oscillator configuration figure 26. timing diagram i d i ds v g.pfc v g.pwm v g.pfc v g.pwm i ds i d figure 27. interleaved leading / trailing edge modulation figure 27 shows the interleaved leading / trailing edge modulation, where the turn-off of the pfc drive signal is synchronized to the turn- on of the pwm drive signal. this technique allows the pfc output diode current to flow directly into the downstream dc/dc converter, minimizing the current ripple of pfc output capacitor. gain modulator gain modulator is the key block for the pfc stage because it provides the refe rence to the current control error amplifier for the input current shaping, as shown in figure 28. the output current of the gain modulator is a function of v ea , i ac, and v rms . the gain of the gain modulator is given as a ratio between i mo and i ac with a given v rms when v ea is saturated to high. the gain is inversely proportional to v rms 2 , as shown in figure 29, to implement line feed-forward. this automatically adjusts the reference of curr ent control error amplifier according to the line voltage, such that the input power of pfc converter is not changed with line voltage (as shown in figure 30). ?? ?? ?? ? 2 (0.6) (0.6) mo ac ea ac max rms ea igi kv i vv figure 28. gain modulator block
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 14 fan4800au/cu ? pfc/ pwm controller combination 2 1 rms g v ? figure 29. modulation gain characteristics v in i l v ea figure 30. line feed-forward operation to sense the rms value of the line voltage, averaging circuit with two poles is typically employed, as shown in figure 28. notice that the i nput voltage of the pfc is clamped at the peak of t he line voltage once the pfc stops switching because the j unction capacitance of the bridge diode is not discharged, as shown in figure 31. therefore, the voltage divider for vrms should be designed considering the brownout protection trip-point and minimum operation line voltage. figure 31. v rms according to the pfc operation the rectified sinusoidal signal is obtained by the current flowing into the iac pin. the resistor r iac should be large enough to prevent saturation of the gain modulator, calculating as: a g r v max iac min line ? 140 2 ? ? (3) where v linemin is the line voltage that trips brownout protection, g max is the maximum modulator gain when v rms is 1.08v (which can be found in the datasheet), and 140a is the maximum output current of the gain modulator. current control of boost stage the fan4800au/cu employs two control loops for power factor correction, as shown in figure 32: a current-control loop and a voltage-control loop. the current-control loop shapes inductor current as shown in figure 33 based on the reference signal obtained at the iac pin calculated as: m ac m mo cs l r g i r i r i ? ? ? ? ? ? 1 (4) figure 32. gain modulation block 1 m mo cs r i r figure 33. inductor current shaping the current-control feedback loop also has a pulse-by- pulse current limit comparat or that forces the pfc switch to turn off until the next switching cycle if the isense pin voltage drops below -1.3v.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 15 fan4800au/cu ? pfc/ pwm controller combination voltage control of boost stage the voltage-control loop regul ates pfc output voltage using an internal error amplifier such that the fb voltage is the same as the internal reference of 2.5v. brownout protection the built-in internal brownout protection comparator monitors the voltage of the vrms pin. once vrms pin voltage is lower than 1.05v, the pfc stage is shut down to protect the system from over current. fan4800au/cu starts up the boost stage once vrms voltage increases above 1.9v. trifault detect? to improve power supply reliability, reduce system component count, and simplif y compliance to ul 1950 safety standards, the fan4800au/cu includes fairchild?s trifault detect technology. in a feedback path failure, th e output voltage of the pfc can exceed safe operating limits. trifaultdetect protects the power supply from a failure related to the output feedback by monitoring the fbpfc voltage. trifaultdetect is an entirely internal circuit. it requires no external components to serve its protective function. v bout r fb1 r fb2 fbpfc disable opfc trifaultdetect + - + - 0.5v 2.75v v dd 300na figure 34. trifault detect? pwm stage the pwm stage is capable of current mode or voltage mode operation. in current-mode, the pwm ramp (ramp) is usually derived directly from a current- sensing resistor or current transformer in the primary side of the output stage, and is thereby representative of the current flowing in the converter?s output stage. i limit , which provides cycle-by-cycle current limiting, is typically connected to ramp in such applications. for voltage-mode operation, ramp can be connected to a separate rc timing network to generate a voltage ramp against which the fbpwm voltage is compared. under these conditions, the voltage feed-forward from the pfc bus can be used for better line transient response. no voltage error amplifier is included in the pwm stage, as this function is generally performed by ka431, in the secondary side. to facilitate the design of opto-coupler feedback circuitry, an offset voltage is built into the inverting input of pwm comparator. this allows fbpwm to command a zero percent duty cycle when its pin voltage is below 1.5v. v bout ramp r ramp c ramp ref + - pwm fbpwm 1.5v figure 35. pwm ramp generation circuit pwm current limit the ilimit pin is a direct input to the cycle-by-cycle current limiter for the pwm se ction. if the input voltage at this pin exceeds 1v, the output of the pwm is disabled for until the start of the next pwm clock cycle. v in ok comparator the v in ok comparator monitors the output of the pfc stage and inhibits the pwm st age if this voltage is less than 2.4v (96% of its nominal value). once this voltage goes above 2.4v, the pwm st age begins soft-start. the pwm stage is shut down when fbpfc voltage drops below 1.3v. pwm soft-start (ss) pwm startup is controlled by the soft-start capacitor. a current source of 10a suppli es the charging current for the soft-start capacitor. pwm startup is prohibited until the soft-start capacitor voltage reaches 1.5v.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 16 fan4800au/cu ? pfc/ pwm controller combination ac line drops out fan4800au/cu is designed such that the operation of pfc part is not perturbed by ac line dropout. once line voltage disappears, the error amplifier can be saturated, resulting in abnormal current waveforms when the line voltage is recovered if prop er preventive measures are not employed. with a limited gain modulator operation, fan4800au /cu guarantees stable pfc operation even when ac line is recovered from dropout, as shown in figure 36. figure 36. ac cycle drop line sag protection when the line sags below its normal operational range, the pfc part keeps operating until the brownout protection is triggered, which has 1s debounce time. due to the low line voltage, the gain modulator for current loop is saturated a nd input current of pfc is limited, resulting in a drop of the pfc output voltage at heavy-load condition. since the pwm part has a v in ok comparator that shuts do wn pwm operation when the fbpfc voltage drops below 1.3v, the downstream dc/dc converter can stop operation while the pfc output voltage drops during line sag. once the downstream converter stops operation, even the limited pfc input current can charge up the pfc output since the pfc part has no load current. because this can cause repeated startup and shutdown of downstream converter during line sag, fan4800au/cu has line sag protection. there are two conditions that trigger line sag protection, as shown in figure 37 and figure 38. the first condition is when v rms is lower than v rms-sag (0.85v) for longer than t sag (33ms), as shown in figure 37. the second condition is when v rms is lower than v rms-sag (0.85v) and vf bpfc is lower than v in-off (1.3v), as shown in figure 38. once line sag protection is triggered, the pwm and the pfc stop operation until v rms increases above 1.9v. figure 37. the first condition of sag protection figure 38. the second condition of sag protection
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 17 fan4800au/cu ? pfc/ pwm controller combination physical dimensions figure 39. 16-pin, dual inline package (dip), jedec ms-001, .300" wide package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 16 9 8 1 notes: unless otherwise specified a this package conforms to jedec ms-001 variation bb b) all dimensions are in millimeters. d) conforms to asme y14.5m-1994 e) drawing file name: n16erev1 19.68 18.66 6.60 6.09 c) dimensions are exclusive of burrs, mold flash, and tie bar protrusions 3.42 3.17 3.81 2.92 (0.40) 2.54 17.78 0.58 0.35 1.78 1.14 5.33 max 0.38 min 8.13 7.62 0.35 0.20 15 0 8.69 a a top view side view
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 18 fan4800au/cu ? pfc/ pwm controller combination physical dimensions figure 40. 16-pin, small-outline integrated circ uit (soic), jedec ms-012, .150", narrow body package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 19 fan4800au/cu ? pfc/ pwm controller combination
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fan4800au/cu ? rev. 1.0.0 20 fan4800au/cu ? pfc/ pwm controller combination
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: fairchild semiconductor: ? fan4800aum? FAN4800AUN? fan4800cum? fan4800cun

▲Up To Search▲

Price & Availability of FAN4800AUN

	To Download FAN4800AUN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .